Hubert Kaeslin: Catalogue data in Spring Semester 2012

Name Prof. em. Dr. Hubert Kaeslin
E-mailkaeslin@retired.ethz.ch
DepartmentInformation Technology and Electrical Engineering
RelationshipRetired Adjunct Professor

NumberTitleECTSHoursLecturers
227-0116-00LVLSI I: From Architectures to VLSI Circuits and FPGAs7 credits5GH. Kaeslin, N. Felber
AbstractUnderstand Very-Large-Scale Integrated Circuits, Application-Specific Integrated Circuits, and Field-Programmable Gate-Arrays. Become fluent in their front-end design from architectural conception down to gate-level netlists. How to model and simulate digital circuits with VHDL. How to take advantage of automatic synthesis tools to produce industrial-quality circuits.
ObjectiveUnderstand Very-Large-Scale Integrated Circuits (VLSI chips), Application-Specific Integrated Circuits (ASIC), and Field-Programmable Gate-Arrays (FPGA). Know their organization and be able to identify suitable application areas. Become fluent in front-end design from architectural conception to gate-level netlists. How to model digital circuits with VHDL. How to ensure they behave as expected with the aid of simulation, testbenches, and assertions. How to take advantage of automatic synthesis tools to produce industrial-quality VLSI and FPGA circuits. Gain practical experience with the hardware description language VHDL and with industrial Electronic Design Automation (EDA) tools.
ContentThis course is concerned with system-level issues of VLSI design and FPGA implementations. Topics include:
- Overview on design methodologies and fabrication depths.
- Levels of abstraction for circuit modeling.
- VLSI and FPGA design flows.
- Dedicated and general purpose architectures compared.
- How to obtain an architecture for a given processing algorithm.
- Meeting throughput, area, and power goals by way of architectural transformations.
- Hardware Description Languages (HDL) and the underlying concepts.
- VHDL (IEEE standard 1076) for simulation and synthesis.
- A suitable nine-valued logic system (IEEE standard 1164).
- Register Transfer Level (RTL) synthesis and its limitations.
- Synchronous versus asynchronous circuits.
- The case for synchronous circuits.
- Periodic events and the Anceau diagram.
- Functional verification of digital integrated circuits.
- Modular and largely reusable testbenches.
- Assertion-based checks.
- Building blocks of digital VLSI circuits.
- Case studies, ASICs compared to microprocessors, DSPs, and FPGAs.

During the exercises, students learn how to model digital ICs with VHDL. They write testbenches for simulation purposes and synthesize gate-level netlists for VLSI chips and FPGAs. Only commercial EDA software by leading vendors is being used.
Literature"Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication" Cambridge University Press, 2008, ISBN 9780521882675.
Prerequisites / NoticePrerequisites:
Basics of digital circuits.

Examination:
In written form following the course semester (spring term). Problems are given in English, answers will be accepted in either English oder German.

Further details:
http://www.iis.ee.ethz.ch/stud_area/vorlesungen/vlsi1.en.html
227-0148-00LVLSI III: Test and Fabrication of VLSI Circuits6 credits4GN. Felber, H. Kaeslin
AbstractKnow how to apply methods, software tools and equipment for designing testable VLSI circuits, for testing fabricated ICs, and for physical analysis in the occurrence of defective parts. A basic understanding of modern semiconductor technologies.
ObjectiveKnow how to apply methods, software tools and equipment for designing testable VLSI circuits, for testing fabricated ICs, and for physical analysis in the occurrence of defective parts. A basic understanding of modern semiconductor technologies.
ContentThis final course in a series of three focusses on manufacturing, testing, physical analysis, and packaging of VLSI circuits. Topics include:
- Effects of fabrication defects.
- Abstraction from physical to transistor- and gate-level fault models.
- Fault grading in the occurrence of large ASICs.
- Generation of efficient test vector sets.
- Enhancement of testability with built-in self test.
- Organisation and application of automated test equipment.
- Physical analysis of devices.
- Packaging problems and solutions.
- Models of industrial cooperation.
- The caveats of virtual components.
- The cost structures of ASIC development and manufacturing.
- Market requirements, decision criteria, and case studies.
- Today's deep-submicron CMOS fabrication processes.
- Outlook on the future evolution of semiconductor technology.

Exercises teach students how to use CAE/CAD software and automated equipment for testing ASICs after fabrication. Students that have submitted a design for manufacturing at the end of the 7th term do so on their own circuits. Physical analysis methods with professional equipment (AFM, DLTS) complement this training.
Lecture notesEnglish lecture notes (Dr. N. Felber).
Literature"Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication" Cambridge University Press, 2008, ISBN 9780521882675 (Dr. H. Kaeslin).
Prerequisites / NoticePrerequisites:
Basic knowledge of digital design.

Further details:
http://www.iis.ee.ethz.ch/stud_area/vorlesungen/vlsi3.en.html