Frank Kagan Gürkaynak: Katalogdaten im Frühjahrssemester 2018

NameHerr Dr. Frank Kagan Gürkaynak
Adresse
Institut für Integrierte Systeme
ETH Zürich, ETZ J 60.1
Gloriastrasse 35
8092 Zürich
SWITZERLAND
Auszeichnung: Die Goldene Eule
Telefon+41 44 632 27 26
E-Mailkgf@ethz.ch
URLhttp://www.iis.ee.ethz.ch/~kgf
DepartementInformationstechnologie und Elektrotechnik
BeziehungDozent

NummerTitelECTSUmfangDozierende
227-0147-00LVLSI II: Design of Very Large Scale Integration Circuits Information 6 KP5GF. K. Gürkaynak, L. Benini
KurzbeschreibungThis second course in our VLSI series is concerned with how to turn digital circuit netlists into safe, testable and manufacturable mask layout, taking into account various parasitic effects. Low-power circuit design is another important topic. Economic aspects and management issues of VLSI projects round off the course.
LernzielKnow how to design digital VLSI circuits that are safe, testable, durable, and make economic sense.
InhaltThe second course begins with a thorough discussion of various technical aspects at the circuit and layout level before moving on to economic issues of VLSI. Topics include:
- The difficulties of finding fabrication defects in large VLSI chips.
- How to make integrated circuit testable (design for test).
- Synchronous clocking disciplines compared, clock skew, clock distribution, input/output timing.
- Synchronization and metastability.
- CMOS transistor-level circuits of gates, flip-flops and random access memories.
- Sinks of energy in CMOS circuits.
- Power estimation and low-power design.
- Current research in low-energy computing.
- Layout parasitics, interconnect delay, static timing analysis.
- Switching currents, ground bounce, IR-drop, power distribution.
- Floorplanning, chip assembly, packaging.
- Layout design at the mask level, physical design verification.
- Electromigration, electrostatic discharge, and latch-up.
- Models of industrial cooperation in microelectronics.
- The caveats of virtual components.
- The cost structures of ASIC development and manufacturing.
- Market requirements, decision criteria, and case studies.
- Yield models.
- Avenues to low-volume fabrication.
- Marketing considerations and case studies.
- Management of VLSI projects.

Exercises are concerned with back-end design (floorplanning, placement, routing, clock and power distribution, layout verification). Industrial CAD tools are being used.
SkriptH. Kaeslin: "Top-Down Digital VLSI Design, from Gate-Level Circuits to CMOS Fabrication", Lecture Notes Vol.2 , 2015.

All written documents in English.
LiteraturH. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.
Voraussetzungen / BesonderesHighlight:
Students are offered the opportunity to design a circuit of their own which then gets actually fabricated as a microchip! Students who elect to participate in this program register for a term project at the Integrated Systems Laboratory in parallel to attending the VLSI II course.

Prerequisites:
"VLSI I: from Architectures to Very Large Scale Integration Circuits and FPGAs" or equivalent knowledge.

Further details:
https://vlsi2.ethz.ch