Luca Benini: Katalogdaten im Frühjahrssemester 2018
|Name||Herr Prof. Dr. Luca Benini|
|Lehrgebiet||Digitale Integrierte Schaltungen und Systeme|
Institut für Integrierte Systeme
ETH Zürich, ETZ J 84
|Telefon||+41 44 632 66 64|
|Departement||Informationstechnologie und Elektrotechnik|
|227-0147-00L||VLSI II: Design of Very Large Scale Integration Circuits||6 KP||5G||F. K. Gürkaynak, L. Benini|
|Kurzbeschreibung||This second course in our VLSI series is concerned with how to turn digital circuit netlists into safe, testable and manufacturable mask layout, taking into account various parasitic effects. Low-power circuit design is another important topic. Economic aspects and management issues of VLSI projects round off the course.|
|Lernziel||Know how to design digital VLSI circuits that are safe, testable, durable, and make economic sense.|
|Inhalt||The second course begins with a thorough discussion of various technical aspects at the circuit and layout level before moving on to economic issues of VLSI. Topics include: |
- The difficulties of finding fabrication defects in large VLSI chips.
- How to make integrated circuit testable (design for test).
- Synchronous clocking disciplines compared, clock skew, clock distribution, input/output timing.
- Synchronization and metastability.
- CMOS transistor-level circuits of gates, flip-flops and random access memories.
- Sinks of energy in CMOS circuits.
- Power estimation and low-power design.
- Current research in low-energy computing.
- Layout parasitics, interconnect delay, static timing analysis.
- Switching currents, ground bounce, IR-drop, power distribution.
- Floorplanning, chip assembly, packaging.
- Layout design at the mask level, physical design verification.
- Electromigration, electrostatic discharge, and latch-up.
- Models of industrial cooperation in microelectronics.
- The caveats of virtual components.
- The cost structures of ASIC development and manufacturing.
- Market requirements, decision criteria, and case studies.
- Yield models.
- Avenues to low-volume fabrication.
- Marketing considerations and case studies.
- Management of VLSI projects.
Exercises are concerned with back-end design (floorplanning, placement, routing, clock and power distribution, layout verification). Industrial CAD tools are being used.
|Skript||H. Kaeslin: "Top-Down Digital VLSI Design, from Gate-Level Circuits to CMOS Fabrication", Lecture Notes Vol.2 , 2015.|
All written documents in English.
|Literatur||H. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.|
|Voraussetzungen / Besonderes||Highlight:|
Students are offered the opportunity to design a circuit of their own which then gets actually fabricated as a microchip! Students who elect to participate in this program register for a term project at the Integrated Systems Laboratory in parallel to attending the VLSI II course.
"VLSI I: from Architectures to Very Large Scale Integration Circuits and FPGAs" or equivalent knowledge.
|227-0150-00L||Energy-Efficient Parallel Computing Systems for Data Analytics |
Previously called "Advanced System-on-chip Design: Integrated Parallel Computing Architectures"
|6 KP||4G||L. Benini|
|Kurzbeschreibung||Advanced Parallel Computing Architectures and related design issues. It will cover multi-cores, many-cores, vector engines, GP-GPUs, application-specific processors and heterogeneous compute accelerators. Focus on integrated architectures for data analytics applications. Special emphasis given to energy-efficiency issues and hardware-software design for power and energy minimizazion.|
|Lernziel||Give in-depth understanding of the links and dependencies between architectures and their energy-efficient implementation and to get a comprehensive exposure to state-of-the-art computing platforma for data anlytics applications. Practical experience will also be gained through practical exercises and mini-projects (hardware and software) assigned on specific topics.|
|Inhalt||The course will cover advanced parallel computing architectures architectures, with an in-depth view on design challenges related to advanced silicon technology and state-of-the-art system integration options (nanometer silicon technology, novel storage devices, three-dimensional integration, advanced system packaging). The emphasis will be on programmable parallel architectures, namely, multi and many- cores, GPUs, vector accelerators, application-specific processors, heterogeneous platforms, and the complex design choices required to achieve scalability and energy proportionality. The course will will also delve into system design, touching on hardware-software tradeoffs and full-system analysis and optimization taking into account non-functional constraints and quality metrics, such as power consumption, thermal dissipation, reliability and variability. The application focus will be on emerging data analytics both in the cloud at at the edges (near-sensor analytics).|
|Skript||Slides will be provided to accompany lectures. Pointers to scientific literature will be given. Exercise scripts and tutorials will be provided.|
|Literatur||D. Patterson, J. Hennessy, Computer Architecture, Fifth Edition: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design), 2011.|
D. Patterson, J. Hennessy, Computer Organization and Design, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design), 2013.
|Voraussetzungen / Besonderes||Knowledge of digital design at the level of "Design of Digital Circuits SS12" is required.|
Knowledge of basic VLSI design at the level of "VLSI I: Architectures of VLSI Circuits" is required