Onur Mutlu: Katalogdaten im Herbstsemester 2018
|Name||Herr Prof. Dr. Onur Mutlu|
ETH Zürich, ETZ G 61.2
|252-3300-00L||Seminar on Computer Architecture |
The deadline for deregistering expires at the end of the second week of the semester. Students who are still registered after that date, but do not attend the seminar, will officially fail the seminar.
|2 KP||2S||O. Mutlu|
|Kurzbeschreibung||In this seminar course, we will cover fundamental and cutting-edge research papers in computer architecture. The course will consist of multiple components that are aimed at improving students' technical skills in computer architecture, critical thinking and analysis on computer architecture concepts, as well as technical presentation of concepts and papers in both spoken and written forms.|
|Lernziel||The main objective is to learn how to rigorously analyze and present papers and ideas computer architecture. We will have rigorous presentation and discussion of selected papers during lectures and a written report delivered by each student at the end of the semester.|
This course is for those interested in computer architecture. Registered students are expected to attend every lecture and participate in the discussion.
|Inhalt||Topics will center around computer architecture. We will, for example, discuss papers on hardware security; architectural acceleration mechanisms for key applications like machine learning, graph processing and bioinformatics; memory systems; interconnects; processing inside memory; various fundamental and emerging paradigms in computer architecture; hardware/software co-design and cooperation; fault tolerance; energy efficiency; heterogeneous and parallel systems; new execution models, etc.|
|Skript||All required materials will be posted on the course website, location to be determined.|
|Literatur||Key papers and articles, on both fundamentals and cutting-edge topics in computer architecture will be provided and discussed. These will be posted on the course website.|
|Voraussetzungen / Besonderes||Design of Digital Circuits.|
Students should have done very well in Design of Digital Circuits and show a genuine interest in Computer Architecture.
|263-2210-00L||Computer Architecture||8 KP||6G + 1A||O. Mutlu|
|Kurzbeschreibung||Computer architecture is the science and art of selecting and interconnecting hardware components to create a computer that meets functional, performance and cost goals. This course introduces the basic components of a modern computing system (processors, memory, interconnects, storage). The course takes a hardware/software cooperative approach to understanding and evaluating computing systems.|
|Lernziel||We will learn the fundamental concepts of the different parts of modern computing systems, as well as the latest trends by exploring the recent research in Industry and Academia. We will extensively cover memory technologies (including DRAM and new Non-Volatile Memory technologies), memory scheduling, parallel computing systems (including multicore processors and GPUs), heterogeneous computing, processing-in-memory, interconnection networks, etc.|
|Inhalt||The principles presented in the lecture are reinforced in the laboratory through the design and simulation of a register transfer (RT) implementation of a MIPS-like pipelined processor in System Verilog. In addition, we will develop a cycle-accurate simulator of this processor in C, and we will use this simulator to explore processor design options.|
|Skript||All the materials (including lecture slides) will be provided on the course website: https://safari.ethz.ch/architecture/|
The video recordings of the lectures are expected to be made available after lectures.
|Literatur||We will provide required and recommended readings in every lecture. They will be mostly recent research papers presented in major Computer Architecture conferences and journals.|
|Voraussetzungen / Besonderes||Design of Digital Circuits|