Onur Mutlu: Catalogue data in Autumn Semester 2020

Name Prof. Dr. Onur Mutlu
FieldComputer Science
Address
Dep. Inf.techno.u.Elektrotechnik
ETH Zürich, ETZ G 61.2
Gloriastrasse 35
8092 Zürich
SWITZERLAND
Telephone+41 44 632 88 53
E-mailonur.mutlu@safari.ethz.ch
URLhttps://people.inf.ethz.ch/omutlu/
DepartmentComputer Science
RelationshipFull Professor

NumberTitleECTSHoursLecturers
227-0085-33LProjects & Seminars: Accelerating Genome Analysis with FPGAs, GPUs, and New Execution Paradigms Restricted registration - show details
Only for Electrical Engineering and Information Technology BSc.

The course unit can only be taken once. Repeated enrollment in a later semester is not creditable.
3 credits3PO. Mutlu
AbstractThe category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.
ObjectiveA genome encodes a set of instructions for performing some functions within our cells. Analyzing our genomes helps, for example, to determine differences in these instructions (known as genetic variations) from human to human that may cause diseases or different traits. One benefit of knowing the genetic variations is better understanding and diagnosis of diseases and the development of efficient drugs.

Computers are widely used to perform genome analysis using dedicated algorithms and data structures. However, timely analysis of genomic data remains a daunting challenge, due to the complex algorithms and large datasets used for the analysis. Increasing the number of processing cores used for genome analysis decreases the overall analysis time, but significantly escalates the cost of building, maintaining, and cooling such a computing cluster, as well as the power/energy consumed by the cluster. This is a critical shortcoming with respect to both energy production and environmental friendliness. Cloud computing platforms can be used as an alternative to distribute the workload, but transferring the data between the clinic and the cloud poses new privacy and legal concerns.

In this course, we will cover the basics of genome analysis to understand the computational steps of the entire pipeline and find the computational bottlenecks. Students will learn about the existing efforts for accelerating one or more of these steps and will have the chance to carry out a hands-on project to improve these efforts.

Prerequisites of the course:
- No prior knowledge in bioinformatics or genome analysis is required.
- Digital Design and Computer Architecture (or equivalent course)
- A good knowledge in C programming language is required.
- Experience in at least one of the following is highly desirable:
FPGA implementation and GPU programming.
- Interest in making things efficient and solving problems

The course is conducted in English.

Course website: https://safari.ethz.ch/projects_and_seminars/doku.php?id=bioinformatics

Learning Materials
===============
1. A survey on accelerating genome analysis: https://arxiv.org/pdf/2008.00961
2. A detailed survey on the state-of-the-art algorithms for sequencing data: https://arxiv.org/pdf/2003.00110
3. An example of how to accelerate genomic sequence matching by two orders of magnitude with the help of FPGAs or GPUs: https://arxiv.org/abs/1910.09020
4. An example of how to accelerate read mapping step by an order of magnitude and without using hardware acceleration: https://arxiv.org/pdf/1912.08735
5. An example of using a different computing paradigm for accelerating read mapping step and improving its energy consumption: https://arxiv.org/pdf/1708.04329
6. Two examples on using software/hardware co-design to accelerate genomic sequence matching by two orders of magnitude: https://arxiv.org/abs/1604.01789 https://arxiv.org/abs/1809.07858
227-0085-34LProjects & Seminars: Designing and Evaluating Memory Systems and Modern Software Workloads with... Restricted registration - show details
Only for Electrical Engineering and Information Technology BSc.

The course unit can only be taken once. Repeated enrollment in a later semester is not creditable.
3 credits3PO. Mutlu
AbstractThe category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.
ObjectiveDRAM is predominantly used to build the main memory systems of modern computing devices. Simulation-based experimental studies are key for understanding the complex interactions between DRAM and modern applications.

Ramulator is an extensible DRAM simulator providing cycle-accurate performance models for a variety of commercial DRAM standards (e.g., DDR3/4, LPDDR3/4, GDDR5, HBM) and academic proposals. Ramulator has a modular design that enables easy integration of additional DRAM standards and mechanisms. Ramulator is written in C++11 and can be easily integrated to full-system simulators such as gem5.

In this P&S, you will design new DRAM and memory controller mechanisms for improving overall system performance, energy consumption, and reliability. You will extend Ramulator with these new designs and evaluate their performance, energy consumption, and reliability using modern applications. This will be the right P&S for you if you would like to learn about the state-of-the-art memory controller and DRAM designs and their interaction with modern applications. This P&S will also enable you to hands-on simulate and understand the memory system behavior of modern workloads such as machine learning, graph analytics, genome analysis.

Prerequisites of the course:
- Digital Design and Computer Architecture (or equivalent course)
- A good knowledge in C/C++ programming language.
- Interest in making things efficient and solving problems.
- Interest in understanding software development and hardware design, and their interactions.

The course is conducted in English.

Course website: https://safari.ethz.ch/projects_and_seminars/doku.php?id=ramulator

Learning Materials
===============
1. An old version of Ramulator:
https://github.com/CMU-SAFARI/ramulator

2. Original Ramulator paper:
https://people.inf.ethz.ch/omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf

3. An example study of modern workloads and DRAM architectures using Ramulator:
https://people.inf.ethz.ch/omutlu/pub/Workload-DRAM-Interaction-Analysis_sigmetrics19_pomacs19.pdf

4. An example recent study of a new DRAM architecture using Ramulator:
https://people.inf.ethz.ch/omutlu/pub/CLR-DRAM_capacity-latency-reconfigurable-DRAM_isca20.pdf

5. An example recent study of a new virtual memory system architecture using Ramulator:
https://people.inf.ethz.ch/omutlu/pub/VBI-virtual-block-interface_isca20.pdf

6. Three examples of new ideas enabled by Ramulator based evaluation
https://people.inf.ethz.ch/omutlu/pub/rowclone_micro13.pdf
https://people.inf.ethz.ch/omutlu/pub/salp-dram_isca12.pdf
https://people.inf.ethz.ch/omutlu/pub/raidr-dram-refresh_isca12.pdf
227-0085-35LProjects & Seminars: Understanding and Improving Modern DRAM Performance, Reliability, and... Restricted registration - show details
Only for Electrical Engineering and Information Technology BSc.

The course unit can only be taken once. Repeated enrollment in a later semester is not creditable.
3 credits3PO. Mutlu
AbstractThe category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.
ObjectiveDRAM is predominantly used to build the main memory systems of modern computing devices. To improve the performance, reliability, and security of DRAM, it is critical to perform experimental characterization and analysis of existing cutting-edge DRAM chips.

SoftMC is an FPGA-based DRAM testing infrastructure that enables the programmer to perform all low-level DRAM operations (i.e., DDR commands) in a cycle-accurate manner. SoftMC provides a simple and intuitive high-level programming interface (in C++) that completely hides the low-level details of the FPGA from programmers. Programmers implement test routines in C++, and the test routines automatically get translated into the low-level SoftMC memory controller operations in the FPGA. SoftMC developers write low-level hardware description language code to enable new and faster studies.

In this P&S, you will have the chance to learn how DRAM is organized and operates in a low-level and gain practical experience in using SoftMC while developing SoftMC programs for new DRAM characterization studies related to performance, reliability and security. You may also improve the SoftMC infrastructure itself to enable new studies. And, who knows, you might discover new security vulnerabilities like RowHammer.

This will be the right P&S for you if you are interested in DRAM technology and would like to learn more about it as well as FPGA technology and how it can be used for practical purposes such as understanding and mitigating RowHammer attacks, generating true random numbers, reducing memory latency, fingerprinting and identifying devices, and improving reliability.

Prerequisites of the course:
- Digital Design and Computer Architecture (or equivalent course)
- Familiarity with FPGA programming
- Interest in low-level hacking and memory
- Interest in discovering why things do or do not work and solving problems

The course is conducted in English.

Course website: https://safari.ethz.ch/projects_and_seminars/doku.php?id=softmc

Learning Materials:
===================
- An old version of SoftMC is here: https://github.com/CMU-SAFARI/SoftMC
- SoftMC description: https://people.inf.ethz.ch/omutlu/pub/softMC_hpca17.pdf
- SoftMC lecture: https://www.youtube.com/watch?v=tnSPEP3t-Ys
- Example RowHammer study using SoftMC: https://people.inf.ethz.ch/omutlu/pub/Revisiting-RowHammer_isca20.pdf
- Example security attack study using SoftMC: https://people.inf.ethz.ch/omutlu/pub/rowhammer-TRRespass_ieee_security_privacy20.pdf
- Example neural network acceleration study using SoftMC: https://people.inf.ethz.ch/omutlu/pub/EDEN-efficient-DNN-inference-with-approximate-memory_micro19.pdf
- Example random number generation study using SoftMC: https://people.inf.ethz.ch/omutlu/pub/drange-dram-latency-based-true-random-number-generator_hpca19.pdf
- Example physical unclonable function study using SoftMC: https://people.inf.ethz.ch/omutlu/pub/dram-latency-puf_hpca18.pdf
- The original RowHammer study using SoftMC: https://people.inf.ethz.ch/omutlu/pub/dram-row-hammer_isca14.pdf
227-0085-36LProjects & Seminars: Genome Sequencing on Mobile Devices Restricted registration - show details
Only for Electrical Engineering and Information Technology BSc.

The course unit can only be taken once. Repeated enrollment in a later semester is not creditable.
3 credits3PO. Mutlu
AbstractThe category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.
ObjectiveGenome analysis is the foundation of many scientific and medical discoveries, and serves as a key enabler of personalized medicine. This analysis is currently limited by the inability of existing technologies to read an organism’s complete genome. Instead, a dedicated machine (called sequencer) extracts a large number of shorter random fragments of an organism’s DNA sequence, known as reads. Small, handheld sequencers such as ONT MinION and Flongle make it possible to sequence bacterial and viral genomes in the field, thus facilitating disease outbreak analyses such as COVID-19, Ebola, and Zika. However, large, capable computers are still needed to perform genome assembly, which tries to reassemble read fragments back into an entire genome sequence. This limits the benefits of mobile sequencing and may pose problems in rapid diagnosis of infectious diseases, tracking outbreaks, and near-patient testing. The problem is exacerbated in developing countries and during crises where access to the internet network, cloud services, or data centers is even more limited.

In this course, we will cover the basics of genome analysis to understand the speed-accuracy tradeoff in using computationally-lightweight heuristics versus accurate computationally-expensive algorithms. Such heuristic algorithms typically operate on a smaller dataset that can fit in the memory of today’s mobile device. Students will experimentally evaluate different heuristic algorithms and observe their effect on the end results. This evaluation will give the students the chance to carry out a hands-on project to implement one or more of these heuristic algorithms in their smartphones and help the society by enabling on-site analysis of genomic data.

Prerequisites of the course:
- No prior knowledge in bioinformatics or genome analysis is required.
- A good knowledge in C programming language and programming is required.
- Interest in making things efficient and solving problems

The course is conducted in English.

Course website: https://safari.ethz.ch/projects_and_seminars/doku.php?id=genome_seq_mobile

Learning Materials
===============
1. A survey on accelerating genome analysis: https://arxiv.org/pdf/2008.00961

2. A detailed survey on the state-of-the-art algorithms for sequencing data: https://arxiv.org/pdf/2003.00110

3. An example of how to accelerate genomic sequence matching by two orders of magnitude with the help of FPGAs or GPUs: https://arxiv.org/abs/1910.09020

4. An example of how to accelerate read mapping step by an order of magnitude and without using hardware acceleration: https://arxiv.org/pdf/1912.08735

5. An example of using a different computing paradigm for accelerating read mapping step and improving its energy consumption: https://arxiv.org/pdf/1708.04329

6. Two examples on using software/hardware co-design to accelerate genomic sequence matching by two orders of magnitude: https://arxiv.org/abs/1604.01789 https://arxiv.org/abs/1809.07858

7. An example of a purely software method for fast genome sequence analysis: http://www.biomedcentral.com/content/pdf/1471-2164-14-S1-S13.pdf
227-0085-37LProjekte & Seminare: Exploring the Processing-in-Memory Paradigm for Future Computing Systems Restricted registration - show details
Only for Electrical Engineering and Information Technology BSc.

The course unit can only be taken once. Repeated enrollment in a later semester is not creditable.
3 credits3PO. Mutlu
AbstractThe category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.
ObjectiveData movement between the memory units and the compute units of current computing systems is a major performance and energy bottleneck. From large-scale servers to mobile devices, data movement costs dominate computation costs in terms of both performance and energy consumption. For example, data movement between the main memory and the processing cores accounts for 62% of the total system energy in consumer applications. As a result, the data movement bottleneck is a huge burden that greatly limits the energy efficiency and performance of modern computing systems. This phenomenon is an undesired effect of the dichotomy between memory and the processor, which leads to the data movement bottleneck.

Many modern and important workloads such as machine learning, computational biology, graph processing, databases, video analytics, and real-time data analytics suffer greatly from the data movement bottleneck. These workloads are exemplified by irregular memory accesses, relatively low data reuse, low cache line utilization, low arithmetic intensity (i.e., ratio of operations per accessed byte), and large datasets that greatly exceed the main memory size. The computation in these workloads cannot usually compensate for the data movement costs. In order to alleviate this data movement bottleneck, we need a paradigm shift from the traditional processor-centric design, where all computation takes place in the compute units, to a more data centric design where processing elements are placed closer to or inside where the data resides. This paradigm of computing is known as Processing-in Memory (PIM).

This is your perfect P&S if you want to become familiar with the main PIM technologies, which represent "the next big thing" in Computer Architecture. You will work hands-on with the first real-world PIM architecture, will explore different PIM architecture designs for important workloads, and will develop tools to enable research of future PIM systems. Projects in this course span software and hardware as well as the software/hardware interface. You can potentially work on developing and optimizing new workloads for the first real world PIM hardware or explore new PIM designs in simulators, or do something else that can forward our understanding of the PIM paradigm.

Prerequisites of the course:
- Digital Design and Computer Architecture (or equivalent course).
- Familiarity with C/C++ programming.
- Interest in future computer architectures and computing paradigms.
- Interest in discovering why things do or do not work and solving problems
- Interest in making systems efficient and usable

The course is conducted in English.

Course website: https://safari.ethz.ch/projects_and_seminars/doku.php?id=processing_in_memory

Learning materials
===============

1. Summary papers about recent research in PIM.
https://people.inf.ethz.ch/omutlu/pub/ProcessingDataWhereItMakesSense_micpro19-invited.pdf
https://people.inf.ethz.ch/omutlu/pub/processing-in-memory_workload-driven-perspective_IBMjrd19.pdf

2. Ramulator-PIM: A version of Ramulator simulator for PIM.
https://github.com/CMU-SAFARI/ramulator-pim

3. UPMEM SDK documentation: The first real-world PIM architecture.
https://sdk.upmem.com/2020.3.0/

4. An example recent study of 3D-stacked PIM for consumer workloads.
https://people.inf.ethz.ch/omutlu/pub/Google-consumer-workloads-data-movement-and-PIM_asplos18.pdf

5. An example recent study of lightweight PIM functionality on 3D-stacked memory:
https://people.inf.ethz.ch/omutlu/pub/pim-enabled-instructons-for-low-overhead-pim_isca15.pdf

6. An example recent study of a PIM accelerator for graph processing.
https://people.inf.ethz.ch/omutlu/pub/tesseract-pim-architecture-for-graph-processing_isca15.pdf

7. An example recent study of a Processing-using-Memory system.
https://people.inf.ethz.ch/omutlu/pub/ambit-bulk-bitwise-dram_micro17.pdf
https://arxiv.org/pdf/1905.09822.pdf
227-2210-00LComputer Architecture Information 8 credits6G + 1AO. Mutlu
AbstractComputer architecture is the science & art of designing and optimizing hardware components and the hardware/software interface to create a computer that meets design goals. This course covers basic components of a modern computing system (processors, memory, interconnects, accelerators). The course takes a hardware/software cooperative approach to understanding and designing computing systems.
ObjectiveWe will learn the fundamental concepts of the different parts of modern computing systems, as well as the latest trends by exploring the recent research in Industry and Academia. We will extensively cover memory technologies (including DRAM and new Non-Volatile Memory technologies), memory scheduling, parallel computing systems (including multicore processors and GPUs), heterogeneous computing, processing-in-memory, interconnection networks, specialized systems for major data-intensive workloads (e.g. graph processing, bioinformatics, machine learning), etc.
ContentThe principles presented in the lecture are reinforced in the laboratory through 1) the design and implementation of a cycle-accurate simulator, where we will explore different components of a modern computing system (e.g., pipeline, memory hierarchy, branch prediction, prefetching, caches, multithreading), and 2) the extension of state-of-the-art research simulators (e.g., Ramulator) for more in-depth understanding of specific system components (e.g., memory scheduling, prefetching).
Lecture notesAll the materials (including lecture slides) will be provided on the course website: https://safari.ethz.ch/architecture/
The video recordings of the lectures are expected to be made available after lectures.
LiteratureWe will provide required and recommended readings in every lecture. They will mainly consist of research papers presented in major Computer Architecture and related conferences and journals.
Prerequisites / NoticeDigital Design and Computer Architecture.
227-2211-00LSeminar in Computer Architecture Information Restricted registration - show details
Number of participants limited to 22.

The deadline for deregistering expires at the end of the second week of the semester. Students who are still registered after that date, but do not attend the seminar, will officially fail the seminar.
2 credits2SO. Mutlu, M. H. K. Alser, J. Gómez Luna
AbstractThis seminar course covers fundamental and cutting-edge research papers in computer architecture. It consists of multiple components that are aimed at improving students' (1) technical skills in computer architecture, (2) critical thinking and analysis abilities on computer architecture concepts, as well as (3) technical presentation of concepts and papers in both spoken and written forms.
ObjectiveThe main objective is to learn how to rigorously analyze and present papers and ideas on computer architecture. We will have rigorous presentation and discussion of selected papers during lectures and a written report delivered by each student at the end of the semester.
This course is for those interested in computer architecture. Registered students are expected to attend every meeting, participate in the discussion, and create a synthesis report at the end of the course.
ContentTopics will center around computer architecture. We will, for example, discuss papers on hardware security; accelerators for key applications like machine learning, graph processing and bioinformatics; memory systems; interconnects; processing in memory; various fundamental and emerging paradigms in computer architecture; hardware/software co-design and cooperation; fault tolerance; energy efficiency; heterogeneous and parallel systems; new execution models; predictable computing, etc.
Lecture notesAll materials will be posted on the course website: https://safari.ethz.ch/architecture_seminar/
Past course materials, including the synthesis report assignment, can be found in the Spring 2020 website for the course: https://safari.ethz.ch/architecture_seminar/spring2020/doku.php?id=start
LiteratureKey papers and articles, on both fundamentals and cutting-edge topics in computer architecture will be provided and discussed. These will be posted on the course website.
Prerequisites / NoticeDigital Design and Computer Architecture.
Students should (1) have done very well in Digital Design and Computer Architecture and (2) show a genuine interest in Computer Architecture.