Onur Mutlu: Katalogdaten im Frühjahrssemester 2021

NameHerr Prof. Dr. Onur Mutlu
LehrgebietInformatik
Adresse
Dep. Inf.techno.u.Elektrotechnik
ETH Zürich, ETZ G 61.2
Gloriastrasse 35
8092 Zürich
SWITZERLAND
Telefon+41 44 632 88 53
E-Mailonur.mutlu@safari.ethz.ch
URLhttps://people.inf.ethz.ch/omutlu/
DepartementInformationstechnologie und Elektrotechnik
BeziehungOrdentlicher Professor

NummerTitelECTSUmfangDozierende
227-0085-34LProjekte & Seminare: Exploring Future Memory Systems with RAMulator Belegung eingeschränkt - Details anzeigen
Nur für Elektrotechnik und Informationstechnologie BSc.

Die Lerneinheit kann nur einmal belegt werden. Eine wiederholte Belegung in einem späteren Semester ist nicht anrechenbar.
3 KP3PO. Mutlu
KurzbeschreibungDer Bereich Praktika, Projekte, Seminare umfasst Lehrveranstaltungen in unterschiedlichen Formaten zum Erwerb von praktischen Kenntnissen und Fertigkeiten. Ausserdem soll selbstständiges Experimentieren und Gestalten gefördert, exploratives Lernen ermöglicht und die Methodik von Projektarbeiten vermittelt werden.
LernzielDRAM is predominantly used to build the main memory systems of modern computing devices. Simulation-based experimental studies are key for understanding the complex interactions between DRAM and modern applications.

Ramulator is an extensible DRAM simulator providing cycle-accurate performance models for a variety of commercial DRAM standards (e.g., DDR3/4, LPDDR3/4, GDDR5, HBM) and academic proposals. Ramulator has a modular design that enables easy integration of additional DRAM standards and mechanisms. Ramulator is written in C++11 and can be easily integrated to full-system simulators such as gem5.

In this P&S, you will design new DRAM and memory controller mechanisms for improving overall system performance, energy consumption, and reliability. You will extend Ramulator with these new designs and evaluate their performance, energy consumption, and reliability using modern applications. This will be the right P&S for you if you would like to learn about the state-of-the-art memory controller and DRAM designs and their interaction with modern applications. This P&S will also enable you to hands-on simulate and understand the memory system behavior of modern workloads such as machine learning, graph analytics, genome analysis.

Prerequisites of the course:
- Digital Design and Computer Architecture (or equivalent course)
- A good knowledge in C/C++ programming language.
- Interest in making things efficient and solving problems.
- Interest in understanding software development and hardware design, and their interactions.

The course is conducted in English.

Course website: https://safari.ethz.ch/projects_and_seminars/doku.php?id=ramulator
227-0085-35LProjekte & Seminare: Enabling Secure, Reliable and Fast Memory with Hands-On FPGA Experiments Belegung eingeschränkt - Details anzeigen
Nur für Elektrotechnik und Informationstechnologie BSc.

Die Lerneinheit kann nur einmal belegt werden. Eine wiederholte Belegung in einem späteren Semester ist nicht anrechenbar.
3 KP3PO. Mutlu
KurzbeschreibungDer Bereich Praktika, Projekte, Seminare umfasst Lehrveranstaltungen in unterschiedlichen Formaten zum Erwerb von praktischen Kenntnissen und Fertigkeiten. Ausserdem soll selbstständiges Experimentieren und Gestalten gefördert, exploratives Lernen ermöglicht und die Methodik von Projektarbeiten vermittelt werden.
LernzielDRAM is predominantly used to build the main memory systems of modern computing devices. To improve the performance, reliability, and security of DRAM, it is critical to perform experimental characterization and analysis of existing cutting-edge DRAM chips.

SoftMC is an FPGA-based DRAM testing infrastructure that enables the programmer to perform all low-level DRAM operations (i.e., DDR commands) in a cycle-accurate manner. SoftMC provides a simple and intuitive high-level programming interface (in C++) that completely hides the low-level details of the FPGA from programmers. Programmers implement test routines in C++, and the test routines automatically get translated into the low-level SoftMC memory controller operations in the FPGA. SoftMC developers write low-level hardware description language code to enable new and faster studies.

In this P&S, you will have the chance to learn how DRAM is organized and operates in a low-level and gain practical experience in using SoftMC while developing SoftMC programs for new DRAM characterization studies related to performance, reliability and security. You may also improve the SoftMC infrastructure itself to enable new studies. And, who knows, you might discover new security vulnerabilities like RowHammer.

This will be the right P&S for you if you are interested in DRAM technology and would like to learn more about it as well as FPGA technology and how it can be used for practical purposes such as understanding and mitigating RowHammer attacks, generating true random numbers, reducing memory latency, fingerprinting and identifying devices, and improving reliability.

Prerequisites of the course:
- Digital Design and Computer Architecture (or equivalent course)
- Familiarity with FPGA programming
- Interest in low-level hacking and memory
- Interest in discovering why things do or do not work and solving problems

The course is conducted in English.

Course website: https://safari.ethz.ch/projects_and_seminars/doku.php?id=softmc
227-0085-44LProjekte & Seminare: Understanding and Designing Modern Solid-State Drives (SSDs) Belegung eingeschränkt - Details anzeigen
Nur für Elektrotechnik und Informationstechnologie BSc.

Die Lerneinheit kann nur einmal belegt werden. Eine wiederholte Belegung in einem späteren Semester ist nicht anrechenbar.
3 KP3PO. Mutlu
KurzbeschreibungDer Bereich Praktika, Projekte, Seminare umfasst Lehrveranstaltungen in unterschiedlichen Formaten zum Erwerb von praktischen Kenntnissen und Fertigkeiten. Ausserdem soll selbstständiges Experimentieren und Gestalten gefördert, exploratives Lernen ermöglicht und die Methodik von Projektarbeiten vermittelt werden.
LernzielNAND flash memory is the de facto standard in architecting a storage device in modern computing systems. As modern computing systems process a large amount of data at an unprecedented scale, a storage device needs to meet high requirements on storage capacity and I/O performance. A NAND flash-based SSD can provide an order(s) of magnitude higher I/O performance compared to traditional hard-disk drives (HDDs), with a much lower cost-per-bit value over any other SSDs based on emerging non-volatile memory (NVM) technologies.

NAND flash memory has several unique characteristics, such as the erase-before write property (i.e., a flash cell needs to be first erased before programming it), limited lifetime (i.e., a cell can reliably store data for a certain number of program/erase cycles), and large operation units (e.g., a NAND flash chip reads/writes data in a page (e.g., 16 KiB) granularity). To achieve high performance and large capacity of the storage system while hiding the unique characteristics of NAND flash memory, it is critical to design efficient SSD firmware, commonly called Flash-Translation Layer (FTL). An FTL is responsible for many critical management tasks, such as address translation, garbage collection, wear-leveling, and I/O scheduling, that significantly affect the performance, reliability, and lifetime of the SSD.

In this P&S, we will cover how a modern NAND flash-based SSD is organized and operates, from the basics of underlying NAND flash devices and various SSD-management tasks at the FTL-level. You will build a practical SSD simulator by refactoring MQSim, a state-of-the-art simulator for high-end SSDs, to support advanced features of modern NAND flash chips and essential SSD-management tasks. This will allow you to have the chance to obtain a comprehensive background of modern storage systems and research experience on system optimization with rigorous evaluation.

Prerequisites of the course:
• No prior knowledge in NAND flash-based storage systems is required.
• Digital Design and Computer Architecture (or equivalent course)
• Good knowledge in C/C++ programming language is required.
• Interest in system optimizations

The course is conducted in English.
227-0085-51LProjekte & Seminare: Hands-on Acceleration on Heterogeneous Computing Systems Belegung eingeschränkt - Details anzeigen
Nur für Elektrotechnik und Informationstechnologie BSc.

Die Lerneinheit kann nur einmal belegt werden. Eine wiederholte Belegung in einem späteren Semester ist nicht anrechenbar.
3 KP3PO. Mutlu, J. Gómez Luna
KurzbeschreibungDer Bereich Praktika, Projekte, Seminare umfasst Lehrveranstaltungen in unterschiedlichen Formaten zum Erwerb von praktischen Kenntnissen und Fertigkeiten. Ausserdem soll selbstständiges Experimentieren und Gestalten gefördert, exploratives Lernen ermöglicht und die Methodik von Projektarbeiten vermittelt werden.
LernzielThe increasing difficulty of scaling the performance and efficiency of CPUs every year has created the need for turning computers into heterogeneous systems, i.e., systems composed of multiple types of processors that can suit better different types of workloads or parts of them. More than a decade ago, Graphics Processing Units (GPUs) became general-purpose parallel processors, in order to make
their outstanding processing capabilities available to many workloads beyond graphics. GPUs have been critical key to the recent rise of Machine Learning and Artificial Intelligence, which took
unrealistic training times before the use of GPUs. Field-Programmable Gate Arrays (FPGAs) are another example computing device that can deliver impressive benefits in terms of performance and energy efficiency. More specific examples are (1) a plethora of specialized accelerators (e.g., Tensor Processing Units for neural networks), and (2) near-data processing architectures (i.e., placing compute capabilities near or inside memory/storage).
Despite the great advances in the adoption of heterogeneous systems in recent years, there are still many challenges to tackle, for example:
- Heterogeneous implementations (using GPUs, FPGAs, TPUs) of modern applications from important fields such as bioinformatics, machine learning, graph processing, medical imaging, personalized medicine, robotics, virtual reality, etc.
- Scheduling techniques for heterogeneous systems with different general-purpose processors and accelerators, e.g., kernel offloading, memory scheduling, etc.
- Workload characterization and programming tools that enable easier and more efficient use of heterogeneous systems.

If you are enthusiastic about working hands-on with different software, hardware, and architecture projects for heterogeneous systems, this is your P&S. You will have the opportunity to program
heterogeneous systems with different types of devices (CPUs, GPUs, FPGAs, TPUs), propose algorithmic changes to important applications to better leverage the compute power of heterogeneous systems, understand different workloads and identify the most suitable device for their execution, design optimized scheduling techniques, etc. In general, the goal will be to reach the highest performance reported for a given important application.
Prerequisites of the course:
- Digital Design and Computer Architecture (or equivalent course).
- Familiarity with C/C++ programming and strong coding skills.
- Interest in future computer architectures and computing paradigms.
- Interest in discovering why things do or do not work and solving problems
- Interest in making systems efficient and usable

The course is conducted in English.
227-2211-00LSeminar in Computer Architecture Information Belegung eingeschränkt - Details anzeigen
Number of participants limited to 22.

The deadline for deregistering expires at the end of the second week of the semester. Students who are still registered after that date, but do not attend the seminar, will officially fail the seminar.
2 KP2SO. Mutlu, M. H. K. Alser, J. Gómez Luna
KurzbeschreibungThis seminar course covers fundamental and cutting-edge research papers in computer architecture. It has multiple components that are aimed at improving students' (1) technical skills in computer architecture, (2) critical thinking and analysis abilities on computer architecture concepts, as well as (3) technical presentation of concepts and papers in both spoken and written forms.
LernzielThe main objective is to learn how to rigorously analyze and present papers and ideas on computer architecture. We will have rigorous presentation and discussion of selected papers during lectures and a written report delivered by each student at the end of the semester.

This course is for those interested in computer architecture. Registered students are expected to attend every meeting, participate in the discussion, and create a synthesis report at the end of the course.
InhaltTopics will center around computer architecture. We will, for example, discuss papers on hardware security; accelerators for key applications like machine learning, graph processing and bioinformatics; memory systems; interconnects; processing in memory; various fundamental and emerging paradigms in computer architecture; hardware/software co-design and cooperation; fault tolerance; energy efficiency; heterogeneous and parallel systems; new execution models; predictable computing, etc.
SkriptAll materials will be posted on the course website: https://safari.ethz.ch/architecture_seminar/
Past course materials, including the synthesis report assignment, can be found in the Fall 2020 website for the course: https://safari.ethz.ch/architecture_seminar/fall2020/doku.php
LiteraturKey papers and articles, on both fundamentals and cutting-edge topics in computer architecture will be provided and discussed. These will be posted on the course website.
Voraussetzungen / BesonderesDesign of Digital Circuits.
Students should (1) have done very well in Design of Digital Circuits and (2) show a genuine interest in Computer Architecture.
252-0028-00LDigital Design and Computer Architecture Information 7 KP4V + 2UO. Mutlu, F. K. Gürkaynak
KurzbeschreibungDiese Lehrveranstaltung ist eine erste Einführung in das Design digitaler Schaltungen und die Computerarchitektur. Sie deckt die technischen Grundlagen wie eine Computerplattform von Grund auf entworfen wird ab. Sie stellt verschiedene Ausführungsparadigmen, Hardwarebeschreibungssprachen und Prinzipien im digitalen Design und der Computerarchitektur vor.
LernzielDiese Lehrveranstaltung ist eine erste Annäherung an die Computerarchitektur. Die Studenten lernen das Design digitaler Schaltkreise, um:
- die Grundlagen,
- die (Design-)Prinzipien,
- und die Präzedenzfälle (in der Computerarchitektur) zu verstehen.
Auf der Grundlage dieses Verständnisses wird von den Studierenden erwartet, dass sie:
- lernen wie ein moderner Computer intern von Grund auf funktioniert,
- die Kompromisse verschiedener Designs und Ideen bewerten können,
- ein fundiertes Design (eines einfachen Mikroprozessors) implementieren können,
- immer komplexere Systeme systematisch austesten können,
- hoffentlich darauf vorbereitet sind, neuartige Out-of-the-Box-Designs zu entwickeln.
Der Fokus liegt auf Grundlagen, Prinzipien, Präzedenzfällen und deren Verwendung um gute Designs zu erstellen/umzusetzen.
InhaltDie Lehrveranstaltung besteht aus den folgenden Hauptblöcken:
- Aktuelle Hauptthemen der Computerarchitektur: Prinzipien, Mysterien, motivierende Fallstudien und Beispiele.
- Digital Logic Design: Kombinationslogik, sequentielle Logik, Hardwarebeschreibungssprachen, FPGAs, Timing und Verifikation.
- Grundlagen der Computerarchitektur: Von Neumann-Computermodell, Befehlssatzarchitektur, Assembly-Programmierung, Mikroarchitektur, Mikroprogrammierung.
- Grundlagen des Prozessordesigns: Pipelining, Out-of-Order-Ausführung, Verzweigungsvorhersage.
- Verarbeitungs-Paradigmen: Out-of-Order-Ausführung, Datenfluss, superskalare Ausführung, VLIW, SIMD-Prozessoren, GPUs, systolische Arrays, Multithreading.
- Speichersystem: Speicherorganisation, Speichertechnologien, Speicherhierarchie, Caches, virtueller Speicher.
SkriptAlle Unterlagen (inklusive Vorlesungsfolien) werden auf der Website der Lehrveranstaltung zur Verfügung gestellt: http://safari.ethz.ch/digitaltechnik/
Die Videoaufzeichnung der Vorlesung wird voraussichtlich bereitgestellt. Es kann dabei zu Verzögerungen kommen.
LiteraturDie offiziellen Lehrbücher dieser Lehrveranstaltung sind “Introduction to Computing Systems” von Patt und Patel, und “Digital Design and Computer Architecture” von Harris und Harris.
Da dieser Kurs auf dem neuesten Stand ist, gibt es kein Lehrbuch das alle Themen abdeckt. Deswegen werden wir die Pflichtlektüre und die empfohlene Literatur für jede Vorlesung bereitstellen. Diese besteht hauptsächlich aus zwei Lehrbüchern und wichtigen Artikeln, die für das Verständnis aktueller Computerarchitekturen essentiell sind.