227-0085-35L  Projects & Seminars: Enabling Secure, Reliable and Fast Memory with Hands-On FPGA Experiments

SemesterSpring Semester 2021
LecturersO. Mutlu
Periodicityevery semester recurring course
Language of instructionEnglish
CommentOnly for Electrical Engineering and Information Technology BSc.

The course unit can only be taken once. Repeated enrollment in a later semester is not creditable.



Courses

NumberTitleHoursLecturers
227-0085-35 PProjekte & Seminare: Enabling Secure, Reliable and Fast Memory with Hands-On FPGA Experiments Special students and auditors need a special permission from the lecturers.
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To access the offer and to enroll for courses log in (with your n.ethz account): https://psapp.ee.ethz.ch/
Please note that the P&S-site is accessible no earlier than two weeks before the start of the semester until four weeks after the start of the semester. Enrollment is only possible from Friday before the start of the semester until noon of the first Friday in the semester.

Time: To be arranged with each student
Location: various
3 hrsO. Mutlu

Catalogue data

AbstractThe category of "Laboratory Courses, Projects, Seminars" includes courses and laboratories in various formats designed to impart practical knowledge and skills. Moreover, these classes encourage independent experimentation and design, allow for explorative learning and teach the methodology of project work.
ObjectiveDRAM is predominantly used to build the main memory systems of modern computing devices. To improve the performance, reliability, and security of DRAM, it is critical to perform experimental characterization and analysis of existing cutting-edge DRAM chips.

SoftMC is an FPGA-based DRAM testing infrastructure that enables the programmer to perform all low-level DRAM operations (i.e., DDR commands) in a cycle-accurate manner. SoftMC provides a simple and intuitive high-level programming interface (in C++) that completely hides the low-level details of the FPGA from programmers. Programmers implement test routines in C++, and the test routines automatically get translated into the low-level SoftMC memory controller operations in the FPGA. SoftMC developers write low-level hardware description language code to enable new and faster studies.

In this P&S, you will have the chance to learn how DRAM is organized and operates in a low-level and gain practical experience in using SoftMC while developing SoftMC programs for new DRAM characterization studies related to performance, reliability and security. You may also improve the SoftMC infrastructure itself to enable new studies. And, who knows, you might discover new security vulnerabilities like RowHammer.

This will be the right P&S for you if you are interested in DRAM technology and would like to learn more about it as well as FPGA technology and how it can be used for practical purposes such as understanding and mitigating RowHammer attacks, generating true random numbers, reducing memory latency, fingerprinting and identifying devices, and improving reliability.

Prerequisites of the course:
- Digital Design and Computer Architecture (or equivalent course)
- Familiarity with FPGA programming
- Interest in low-level hacking and memory
- Interest in discovering why things do or do not work and solving problems

The course is conducted in English.

Course website: https://safari.ethz.ch/projects_and_seminars/doku.php?id=softmc

Performance assessment

Performance assessment information (valid until the course unit is held again)
Performance assessment as a semester course
ECTS credits3 credits
ExaminersO. Mutlu
Typeungraded semester performance
Language of examinationEnglish
RepetitionRepetition only possible after re-enrolling for the course unit.

Learning materials

No public learning materials available.
Only public learning materials are listed.

Groups

No information on groups available.

Restrictions

General : Special students and auditors need a special permission from the lecturers
PlacesLimited number of places. Special selection procedure.
Beginning of registration periodRegistration possible from 19.02.2021
PriorityRegistration for the course unit is only possible for the primary target group
Primary target groupElectrical Engin. + Information Technology BSc (228000)
Waiting listuntil 12.03.2021
End of registration periodRegistration only possible until 05.03.2021

Offered in

ProgrammeSectionType
Electrical Engineering and Information Technology BachelorProjects & SeminarsWInformation