227-0147-00L VLSI II: Design of Very Large Scale Integration Circuits
|Semester||Autumn Semester 2014|
|Lecturers||H. Kaeslin, N. Felber|
|Periodicity||yearly recurring course|
|Language of instruction||English|
|Abstract||This second course in our VLSI series is concerned with how to turn digital netlists into safe, testable and manufacturable mask layout, taking into account various parasitic effects (clock skew, metastability, ground bounce, IR-drop, electromigration, ESD, latchup). Economic aspects and management issues of VLSI projects are also addressed.|
|Objective||Know how to design digital VLSI circuits that are safe, testable, durable, and make economic sense.|
|Content||The second course begins with a thorough discussion of various technical aspects at the circuit and layout level before moving on to economic issues of VLSI. Topics include: |
- Limitations of functional design verification, design for test.
- Synchronous clocking disciplines compared, clock skew, clock distribution, input/output timing.
- Synchronization and metastability.
- CMOS transistor-level circuits of gates, flip-flops and random access memories.
- Sinks of energy in CMOS circuits.
- Power estimation and low-power design.
- Current research in low-energy computing.
- Layout parasitics, interconnect delay, static timing analysis.
- Switching currents, ground bounce, IR-drop, power distribution.
- Floorplanning, chip assembly, packaging.
- Layout design at the mask level, physical design verification.
- Electromigration, electrostatic discharge, and latch-up.
- Models of industrial cooperation in microelectronics.
- The caveats of virtual components.
- The cost structures of ASIC development and manufacturing.
- Market requirements, decision criteria, and case studies.
- Yield models.
- Avenues to low-volume fabrication.
- Marketing aspects and case studies.
- Management of VLSI projects.
Exercises are concerned with back-end design (floorplanning, placement, routing, clock and power distribution, layout verification). Industrial CAD tools are being used.
|Lecture notes||English lecture notes.|
All written documents in English.
|Literature||H. Kaeslin: "Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication" Cambridge University Press, 2008, ISBN 9780521882675|
|Prerequisites / Notice||Highlight:|
Students are offered the opportunity to design a circuit of their own which then gets actually fabricated as a microchip! Students who elect to participate in this program register for a term project at the Integrated Systems Laboratory in parallel to attending the VLSI II course.
"VLSI I: from Architectures to Very Large Scale Integration Circuits and FPGAs" or equivalent knowledge.