227-0150-00L  Advanced System-on-chip Design: Integrated Parallel Computing Architectures

SemesterFrühjahrssemester 2015
DozierendeL. Benini
Periodizitätjährlich wiederkehrende Veranstaltung
LehrspracheEnglisch



Lehrveranstaltungen

NummerTitelUmfangDozierende
227-0150-00 GAdvanced System-on-chip Design: Integrated Parallel Computing Architectures4 Std.
Di08:15-12:00ETZ E 9 »
L. Benini

Katalogdaten

KurzbeschreibungThe course will cover Digital System-on-Chip architectures: multi-cores, many-cores, GP-GPUs and heterogeneous platforms, with an in-depth view on design tools and methods targeting advanced nanometer-scale technology and system integration options.
LernzielTo provide an in-depth understanding of the links and dependencies between architectures and their silicon implementation and to get an
exposure to state-of-the-art methodologies for designing complex integrated systems using advanced technologies. Practical experience will also be gained through projects assigned on specific topics.
InhaltThe course will cover Digital System-on-Chip architectures, design tools and methods, with an in-depth view on design challenges related to advanced silicon technology and state-of-the-art system integration options (novel storage options, three-dimensional integration, advanced system packaging). The emphasis will be on programmable parallel architectures, namely, multi and many- cores, GPUs, vector accelerators, heterogeneous platforms, and the complex design choices required to achieve scalability and energy proportionality. The course will cover not only circuit, logic and microarchitecture design, but it will also delve into system design, touching on hardware-software tradeoffs and full-system analysis and optimization taking into account non-functional constraints and quality metrics, such as power consumption, thermal dissipation, reliability and variability.
SkriptSlides will be provided to accompany lectures
LiteraturD. Patterson, J. Hennessy, Computer Architecture, Fifth Edition: A Quantitative Approach (The Morgan Kaufmann Series in Computer Architecture and Design), 2011.

D. Patterson, J. Hennessy, Computer Organization and Design, Fifth Edition: The Hardware/Software Interface (The Morgan Kaufmann Series in Computer Architecture and Design), 2013.
Voraussetzungen / BesonderesKnowledge of digital design at the level of "Design of Digital Circuits SS12" is required.

Knowledge of basic VLSI design at the level of "VLSI I: Architectures of VLSI Circuits" is required

Leistungskontrolle

Information zur Leistungskontrolle (gültig bis die Lerneinheit neu gelesen wird)
Leistungskontrolle als Semesterkurs
ECTS Kreditpunkte6 KP
PrüfendeL. Benini
FormSessionsprüfung
PrüfungsspracheEnglisch
RepetitionDie Leistungskontrolle wird in jeder Session angeboten. Die Repetition ist ohne erneute Belegung der Lerneinheit möglich.
Prüfungsmodusmündlich 30 Minuten
Diese Angaben können noch zu Semesterbeginn aktualisiert werden; verbindlich sind die Angaben auf dem Prüfungsplan.

Lernmaterialien

 
HauptlinkCourse Homepage
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StudiengangBereichTyp
Elektrotechnik und Informationstechnologie MasterKernfächerWInformation