Frank Kagan Gürkaynak: Catalogue data in Spring Semester 2022

Name	Mr Frank Kagan Gürkaynak
Address	Institut für Integrierte Systeme ETH Zürich, ETZ J 60.1 Gloriastrasse 35 8092 Zürich SWITZERLAND
Telephone	+41 44 632 27 26
E-mail	kgf@ethz.ch
URL	http://www.iis.ee.ethz.ch/~kgf
Department	Information Technology and Electrical Engineering
Relationship	Lecturer

Number	Title	ECTS	Hours	Lecturers
227-0147-00L	VLSI 2: From Netlist to Complete System on Chip	6 credits	5G	F. K. Gürkaynak, L. Benini
Abstract	This second course in our VLSI series is concerned with how to turn digital circuit netlists into safe, testable and manufacturable mask layout, taking into account various parasitic effects. Low-power circuit design is another important topic. Economic aspects and management issues of VLSI projects round off the course.
Learning objective	Know how to design digital VLSI circuits that are safe, testable, durable, and make economic sense.
Content	The second course begins with a thorough discussion of various technical aspects at the circuit and layout level before moving on to economic issues of VLSI. Topics include: - The difficulties of finding fabrication defects in large VLSI chips. - How to make integrated circuit testable (design for test). - Synchronous clocking disciplines compared, clock skew, clock distribution, input/output timing. - Synchronization and metastability. - CMOS transistor-level circuits of gates, flip-flops and random access memories. - Sinks of energy in CMOS circuits. - Power estimation and low-power design. - Current research in low-energy computing. - Layout parasitics, interconnect delay, static timing analysis. - Switching currents, ground bounce, IR-drop, power distribution. - Floorplanning, chip assembly, packaging. - Layout design at the mask level, physical design verification. - Electromigration, electrostatic discharge, and latch-up. - Models of industrial cooperation in microelectronics. - The caveats of virtual components. - The cost structures of ASIC development and manufacturing. - Market requirements, decision criteria, and case studies. - Yield models. - Avenues to low-volume fabrication. - Marketing considerations and case studies. - Management of VLSI projects. Exercises are concerned with back-end design (floorplanning, placement, routing, clock and power distribution, layout verification). Industrial CAD tools are being used.
Lecture notes	H. Kaeslin: "Top-Down Digital VLSI Design, from Gate-Level Circuits to CMOS Fabrication", Lecture Notes Vol.2 , 2015. All written documents in English.
Literature	H. Kaeslin: "Top-Down Digital VLSI Design, from Architectures to Gate-Level Circuits and FPGAs", Elsevier, 2014, ISBN 9780128007303.
Prerequisites / Notice	Highlight: Students are offered the opportunity to design a circuit of their own which then gets actually fabricated as a microchip! Students who elect to participate in this program register for a term project at the Integrated Systems Laboratory in parallel to attending the VLSI II course. Prerequisites: "VLSI I: from Architectures to Very Large Scale Integration Circuits and FPGAs" or equivalent knowledge. Further details: https://vlsi2.ethz.ch
227-0148-00L	VLSI 4: Practical VLSI: Measurement and Testing Formerly (until AS 2021) named "VLSI III: Test and Fabrication of VLSI Circuits", the content has been slightly adapted.	6 credits	4G	F. K. Gürkaynak, L. Benini
Abstract	In this revamped course, we will concentrate on practical aspects of modern integrated circuit testing with an emphasis on hands-on-experience on an IC tester. This will help students to better understand several aspects that have been highlighted in previous VLSI lecture series and allow them to test their own ICs designed during prior semester/bachelor theses.
Learning objective	In this course, students will: - Get hands-on experience working in a modern IC Test laboratory and learn the steps needed to bring-up, characterize and test digital integrated circuits. - Develop problem solving skills and get experience in approaching issues that involve many different engineering steps. - Gather first hand experience how Design-For-Test (DFT) methodologies help for IC Design, and understand the trade-offs between performance and testability. - Learn about challenges of IC Manufacturing process, and what kind of failures can be encountered, and get a deeper understanding of IC Design process - For students that have worked on a prior bachelor/semester thesis on an IC design project, allow them to test their own IC.
Content	If you want to earn money by selling ICs, you will have to deliver a product that will function properly with a very large probability. This lecture will be discussing how this can be achieved. The main point of emphasis will be hands-on-exercises on a state-of-the-art automated test equipment (Advantest SoC V93000) where students will work in groups of two (or maximum three). Students will be able to schedule their exercises so that it fits their individual schedule. There will also be concentrated classroom lectures that will convey the necessary information that students will need for the exercises which will cover aspects of - Economics of testing - CMOS manufacturing and fault models, stuck at faults - Automated Test Equipment - Measuring timing and power - Testing of memories - Built in Self-Test (BIST) There will be 10 lectures (some weeks will be lecture free, exact schedule to be communicated) and 8 exercises. The final exercise will involve individual work where students test an IC with the knowledge they gained from previous exercises. Students that complete this exercise and present a test report (4-10 pages) will pass the course. Please note that the exercises in this class are involved and will require you to make preparations in advance. Expect to spend at least 4 hours of your own time for exercise preparations, and expect at least three individual half day sessions for the final exercise where you test the IC to qualify for a passing grade. It will be possible to finish the exercises until the end of July.
Lecture notes	The following book will accompany students during the lecture: "Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits" by Michael L. Bushnell and Vishwani D. Agrawal, Springer, 2004. This book is available online within ETH through http://link.springer.com/book/10.1007%2Fb117406
Literature	Course website: https://vlsi4.ethz.ch
Prerequisites / Notice	VLSI4 is meant for students interested in digital IC Design and especially for students that are planning or have already done a bachelor/semester thesis on IC Design. Although not strictly necessary, VLSI2 would be quite helpful for students visiting this lecture, VLSI2 and VLSI4 can be visited at the same time. Other lectures of the VLSI series (VLSI1, VLSI3) are not needed to follow VLSI4. Course website for up to date information: https://vlsi4.ethz.ch
247-0302-00L	Integrated Circuits (ICs) Only for CAS in Applied Electronics and Digitization and MAS in Applied Technology.	3 credits	2G	F. K. Gürkaynak
Abstract	This course will expose participants to the full design cycle and cost-performance relationships for integrated circuits (ICs) used in machine learning and cryptographic applications.
Learning objective	The aim of this course is to enable participants to work effectively with design engineers as they make business decisions regarding technical trade-offs in IC chip design.
252-0028-00L	Digital Design and Computer Architecture	7 credits	4V + 2U	O. Mutlu, F. K. Gürkaynak
Abstract	The class provides a first introduction to the design of digital circuits and computer architecture. It covers technical foundations of how a computing platform is designed from the bottom up. It introduces various execution paradigms, hardware description languages, and principles in digital design and computer architecture.
Learning objective	This class provides a first approach to Computer Architecture. The students learn the design of digital circuits in order to: - understand the basics, - understand the principles (of design), - understand the precedents (in computer architecture). Based on such understanding, the students are expected to: - learn how a modern computer works underneath, from the bottom up, - evaluate tradeoffs of different designs and ideas, - implement a principled design (a simple microprocessor), - learn to systematically debug increasingly complex systems, - hopefully be prepared to develop novel, out-of-the-box designs. The focus is on basics, principles, precedents, and how to use them to create/implement good designs.
Content	The class consists of the following major blocks of contents: - Major Current Issues in Computer Architecture: Principles, Mysteries, Motivational Case Studies and Examples - Digital Logic Design: Combinational Logic, Sequential Logic, Hardware Description Languages, FPGAs, Timing and Verification. - Basics of Computer Architecture: Von Neumann Model of Computing, Instruction Set Architecture, Assembly Programming, Microarchitecture, Microprogramming. - Basics of Processor Design: Pipelining, Out-of-Order Execution, Branch Prediction. - Execution Paradigms: Out-of-order Execution, Dataflow, Superscalar Execution, VLIW, Decoupled Access/Execute, SIMD Processors, GPUs, Systolic Arrays, Multithreading. - Memory System: Memory Organization, Memory Technologies, Memory Hierarchy, Caches, Prefetching, Virtual Memory.
Lecture notes	All the materials (including lecture slides) will be provided on the course website: http://safari.ethz.ch/digitaltechnik/ The video recordings of the lectures are likely to be made available, but there may be delays associated with the posting of online videos.
Literature	Patt and Patel's "Introduction to Computing Systems" and Harris and Harris's "Digital Design and Computer Architecture" are the official textbooks of the course. We will provide required and recommended readings in every lecture since the course is cutting-edge and there is no textbook that covers what the course covers. They will be mostly chapters of the two textbooks, and important articles that are essential for understanding the material.