Onur Mutlu: Katalogdaten im Frühjahrssemester 2022 |
| Name | Herr Prof. Dr. Onur Mutlu |
| Lehrgebiet | Informatik |
| Adresse | Dep. Inf.techno.u.Elektrotechnik ETH Zürich, ETZ F 84 Gloriastrasse 35 8092 Zürich SWITZERLAND |
| onur.mutlu@safari.ethz.ch | |
| URL | https://people.inf.ethz.ch/omutlu/ |
| Departement | Informationstechnologie und Elektrotechnik |
| Beziehung | Ordentlicher Professor |
| Nummer | Titel | ECTS | Umfang | Dozierende | |
|---|---|---|---|---|---|
| 227-0085-51L | Projekte & Seminare: Hands-on Acceleration on Heterogeneous Computing Systems  Nur für Elektrotechnik und Informationstechnologie BSc. Die Lerneinheit kann nur einmal belegt werden. Eine wiederholte Belegung in einem späteren Semester ist nicht anrechenbar. | 3 KP | 3P | O. Mutlu, J. Gómez Luna | |
| Kurzbeschreibung | Der Bereich Praktika, Projekte, Seminare umfasst Lehrveranstaltungen in unterschiedlichen Formaten zum Erwerb von praktischen Kenntnissen und Fertigkeiten. Ausserdem soll selbstständiges Experimentieren und Gestalten gefördert, exploratives Lernen ermöglicht und die Methodik von Projektarbeiten vermittelt werden. | ||||
| Lernziel | The increasing difficulty of scaling the performance and efficiency of CPUs every year has created the need for turning computers into heterogeneous systems, i.e., systems composed of multiple types of processors that can suit better different types of workloads or parts of them. More than a decade ago, Graphics Processing Units (GPUs) became general-purpose parallel processors, in order to make their outstanding processing capabilities available to many workloads beyond graphics. GPUs have been critical key to the recent rise of Machine Learning and Artificial Intelligence, which took unrealistic training times before the use of GPUs. Field-Programmable Gate Arrays (FPGAs) are another example computing device that can deliver impressive benefits in terms of performance and energy efficiency. More specific examples are (1) a plethora of specialized accelerators (e.g., Tensor Processing Units for neural networks), and (2) near-data processing architectures (i.e., placing compute capabilities near or inside memory/storage). Despite the great advances in the adoption of heterogeneous systems in recent years, there are still many challenges to tackle, for example: - Heterogeneous implementations (using GPUs, FPGAs, TPUs) of modern applications from important fields such as bioinformatics, machine learning, graph processing, medical imaging, personalized medicine, robotics, virtual reality, etc. - Scheduling techniques for heterogeneous systems with different general-purpose processors and accelerators, e.g., kernel offloading, memory scheduling, etc. - Workload characterization and programming tools that enable easier and more efficient use of heterogeneous systems. If you are enthusiastic about working hands-on with different software, hardware, and architecture projects for heterogeneous systems, this is your P&S. You will have the opportunity to program heterogeneous systems with different types of devices (CPUs, GPUs, FPGAs, TPUs), propose algorithmic changes to important applications to better leverage the compute power of heterogeneous systems, understand different workloads and identify the most suitable device for their execution, design optimized scheduling techniques, etc. In general, the goal will be to reach the highest performance reported for a given important application. Prerequisites of the course: - Digital Design and Computer Architecture (or equivalent course). - Familiarity with C/C++ programming and strong coding skills. - Interest in future computer architectures and computing paradigms. - Interest in discovering why things do or do not work and solving problems - Interest in making systems efficient and usable The course is conducted in English. The course has two main parts: 1. Weekly lectures on GPU and heterogeneous programming. 2. Hands-on project: Each student develops his/her own project. | ||||
| 227-0085-56L | Projekte & Seminare: Intelligent Architectures via Hardware/Software Cooperation Nur für Elektrotechnik und Informationstechnologie BSc. Die Lerneinheit kann nur einmal belegt werden. Eine wiederholte Belegung in einem späteren Semester ist nicht anrechenbar. | 3 KP | 3P | O. Mutlu | |
| Kurzbeschreibung | Der Bereich Praktika, Projekte, Seminare umfasst Lehrveranstaltungen in unterschiedlichen Formaten zum Erwerb von praktischen Kenntnissen und Fertigkeiten. Ausserdem soll selbstständiges Experimentieren und Gestalten gefördert, exploratives Lernen ermöglicht und die Methodik von Projektarbeiten vermittelt werden. | ||||
| Lernziel | Modern general-purpose processors are agnostic to an application’s high-level semantic information. Hence, they employ prediction-based techniques to enable computational and memory optimizations, such as prefetching, cache management policies, memory data placement, instruction scheduling, and many others. As such, the potential of such optimizations is limited due to the limited information the underlying hardware can discover on its own and such optimizations come with large area, power and complexity overheads required by the hardware for prediction purposes. Purely-hardware optimizations cannot achieve their performance potential and waste power, complexity and hardware area, since they are not aware of the application characteristics. On the other hand, purely-software optimizations are fundamentally tied up and limited by the underlying hardware. A promising way to increase the performance of modern applications is to co-design software and hardware. Hence, lately both industry and academia are making serious attempts to improve performance, energy and security using hardware/software cooperative schemes such as application-specific hardware accelerators (e.g., Google’s Tensor Processing Unit) and application-specific extensions in general-purpose processors (e.g., Media Engine in Apple M1). In this course, we will explore several different topics around hardware/software co-design such as: (i) new hardware/software interfaces (e.g., virtual memory, instruction set architecture) to enhance performance, energy and security, (ii) hardware/software co-design schemes to improve the performance of the memory subsystem in killer memory-intensive applications (e.g., sparse and irregular workloads), (iii) hardware/software cooperative machine-learning-based techniques for different microarchitectural components such as prefetchers, caches and branch predictors, which would continuously learn from the vast amount of memory accesses seen by a processor and adapt to the varying workload and system conditions. If you are enthusiastic about working hands-on to design both software and hardware, this is your P&S. You will have the opportunity to study modern applications, propose software changes to better match the underlying hardware components, design new hardware components that better match the overlying software and come up with new machine-learning techniques to design efficient microarchitectural components. You will also learn how to program industry-supported microarchitectural simulators and study the performance of modern workloads after your hardware/software modifications. Prerequisites of the course: - Digital Design and Computer Architecture (or equivalent course). - Familiarity with C/C++ programming and strong coding skills. - Interest in future computer architectures and computing paradigms. - Interest in discovering why things do or do not work and solving problems - Interest in making systems efficient and usable Preferable: - Hands-on experience with Machine Learning frameworks (depends on the topic you choose) The course is conducted in English. | ||||
| 227-2211-00L | Seminar in Computer Architecture  Number of participants limited to 22. The deadline for deregistering expires at the end of the second week of the semester. Students who are still registered after that date, but do not attend the seminar, will officially fail the seminar. | 2 KP | 2S | O. Mutlu, M. H. K. Alser, J. Gómez Luna | |
| Kurzbeschreibung | This seminar course covers fundamental and cutting-edge research papers in computer architecture. It has multiple components that are aimed at improving students' (1) technical skills in computer architecture, (2) critical thinking and analysis abilities on computer architecture concepts, as well as (3) technical presentation of concepts and papers in both spoken and written forms. | ||||
| Lernziel | The main objective is to learn how to rigorously analyze and present papers and ideas on computer architecture. We will have rigorous presentation and discussion of selected papers during lectures and a written report delivered by each student at the end of the semester. This course is for those interested in computer architecture. Registered students are expected to attend every meeting, participate in the discussion, and create a synthesis report at the end of the course. | ||||
| Inhalt | Topics will center around computer architecture. We will, for example, discuss papers on hardware security; accelerators for key applications like machine learning, graph processing and bioinformatics; memory systems; interconnects; processing in memory; various fundamental and emerging paradigms in computer architecture; hardware/software co-design and cooperation; fault tolerance; energy efficiency; heterogeneous and parallel systems; new execution models; predictable computing, etc. | ||||
| Skript | All materials will be posted on the course website: https://safari.ethz.ch/architecture_seminar/ Past course materials, including the synthesis report assignment, can be found in the Fall 2020 website for the course: https://safari.ethz.ch/architecture_seminar/fall2020/doku.php | ||||
| Literatur | Key papers and articles, on both fundamentals and cutting-edge topics in computer architecture will be provided and discussed. These will be posted on the course website. | ||||
| Voraussetzungen / Besonderes | Design of Digital Circuits. Students should (1) have done very well in Design of Digital Circuits and (2) show a genuine interest in Computer Architecture. | ||||
| 252-0028-00L | Digital Design and Computer Architecture | 7 KP | 4V + 2U | O. Mutlu, F. K. Gürkaynak | |
| Kurzbeschreibung | Diese Lehrveranstaltung ist eine erste Einführung in das Design digitaler Schaltungen und die Computerarchitektur. Sie deckt die technischen Grundlagen wie eine Computerplattform von Grund auf entworfen wird ab. Sie stellt verschiedene Ausführungsparadigmen, Hardwarebeschreibungssprachen und Prinzipien im digitalen Design und der Computerarchitektur vor. | ||||
| Lernziel | Diese Lehrveranstaltung ist eine erste Annäherung an die Computerarchitektur. Die Studenten lernen das Design digitaler Schaltkreise, um: - die Grundlagen, - die (Design-)Prinzipien, - und die Präzedenzfälle (in der Computerarchitektur) zu verstehen. Auf der Grundlage dieses Verständnisses wird von den Studierenden erwartet, dass sie: - lernen wie ein moderner Computer intern von Grund auf funktioniert, - die Kompromisse verschiedener Designs und Ideen bewerten können, - ein fundiertes Design (eines einfachen Mikroprozessors) implementieren können, - immer komplexere Systeme systematisch austesten können, - hoffentlich darauf vorbereitet sind, neuartige Out-of-the-Box-Designs zu entwickeln. Der Fokus liegt auf Grundlagen, Prinzipien, Präzedenzfällen und deren Verwendung um gute Designs zu erstellen/umzusetzen. | ||||
| Inhalt | Die Lehrveranstaltung besteht aus den folgenden Hauptblöcken: - Aktuelle Hauptthemen der Computerarchitektur: Prinzipien, Mysterien, motivierende Fallstudien und Beispiele. - Digital Logic Design: Kombinationslogik, sequentielle Logik, Hardwarebeschreibungssprachen, FPGAs, Timing und Verifikation. - Grundlagen der Computerarchitektur: Von Neumann-Computermodell, Befehlssatzarchitektur, Assembly-Programmierung, Mikroarchitektur, Mikroprogrammierung. - Grundlagen des Prozessordesigns: Pipelining, Out-of-Order-Ausführung, Verzweigungsvorhersage. - Verarbeitungs-Paradigmen: Out-of-Order-Ausführung, Datenfluss, superskalare Ausführung, Decoupled Access/Execute, VLIW, SIMD-Prozessoren, GPUs, systolische Arrays, Multithreading. - Speichersystem: Speicherorganisation, Speichertechnologien, Speicherhierarchie, Caches, Prefetching, virtueller Speicher. | ||||
| Skript | Alle Unterlagen (inklusive Vorlesungsfolien) werden auf der Website der Lehrveranstaltung zur Verfügung gestellt: http://safari.ethz.ch/digitaltechnik/ Die Videoaufzeichnung der Vorlesung wird voraussichtlich bereitgestellt. Es kann dabei zu Verzögerungen kommen. | ||||
| Literatur | Die offiziellen Lehrbücher dieser Lehrveranstaltung sind “Introduction to Computing Systems” von Patt und Patel, und “Digital Design and Computer Architecture” von Harris und Harris. Da dieser Kurs auf dem neuesten Stand ist, gibt es kein Lehrbuch das alle Themen abdeckt. Deswegen werden wir die Pflichtlektüre und die empfohlene Literatur für jede Vorlesung bereitstellen. Diese besteht hauptsächlich aus zwei Lehrbüchern und wichtigen Artikeln, die für das Verständnis aktueller Computerarchitekturen essentiell sind. | ||||