Juan Gómez Luna: Catalogue data in Autumn Semester 2023 |
| Name | Dr. Juan Gómez Luna |
| Department | Information Technology and Electrical Engineering |
| Relationship | Lecturer |
| Number | Title | ECTS | Hours | Lecturers | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 227-2210-00L | Computer Architecture  | 8 credits | 6G + 1A | S. Sadrosadati, J. Gómez Luna, O. Mutlu | |||||||||||||||||||||||||||||
| Abstract | Computer architecture is the science & art of designing and optimizing hardware components and the hardware/software interface to create a computer that meets design goals. This course covers basic components of a modern computing system (memory, processors, interconnects, accelerators). The course takes a hardware/software cooperative approach to understanding and designing computing systems. | ||||||||||||||||||||||||||||||||
| Learning objective | We will learn the fundamental concepts of the different parts of modern computing systems, as well as the latest major research topics in Industry and Academia. We will extensively cover memory systems (including DRAM and new Non-Volatile Memory technologies, memory controllers, flash memory), new paradigms like processing-in-memory, parallel computing systems (including multicore processors, coherence and consistency, GPUs), heterogeneous computing, interconnection networks, specialized systems for major data-intensive workloads (e.g. graph analytics, bioinformatics, machine learning), etc. We will focus on fundamentals as well as cutting-edge research. Significant attention will be given to real-life examples and tradeoffs, as well as critical analysis of modern computing systems. | ||||||||||||||||||||||||||||||||
| Content | The principles presented in the lecture are reinforced in the laboratory through 1) the design and implementation of a cycle-accurate simulator, where we will explore different components of a modern computing system (e.g., pipeline, memory hierarchy, branch prediction, prefetching, caches, multithreading), and 2) the extension of state-of-the-art research simulators (e.g., Ramulator) for more in-depth understanding of specific system components (e.g., memory scheduling, prefetching). See the course website for detailed and complete content of past incarnations of the course: https://safari.ethz.ch/architecture | ||||||||||||||||||||||||||||||||
| Lecture notes | All the materials (including lecture slides) will be provided on the course website: https://safari.ethz.ch/architecture/ The video recordings of the lectures are expected to be made available after lectures. See https://safari.ethz.ch/architecture for past examples. | ||||||||||||||||||||||||||||||||
| Literature | We will provide required and recommended readings in every lecture. They will mainly consist of research papers presented in major Computer Architecture and related conferences and journals. See https://safari.ethz.ch/architecture for past examples. | ||||||||||||||||||||||||||||||||
| Prerequisites / Notice | Digital Design and Computer Architecture (https://safari.ethz.ch/digitaltechnik) | ||||||||||||||||||||||||||||||||
| Competencies |
| ||||||||||||||||||||||||||||||||
| 227-2211-00L | Seminar in Computer Architecture  The deadline for deregistering expires at the end of the second week of the semester. Students who are still registered after that date, but do not attend the seminar, will officially fail the seminar. | 2 credits | 2S | S. Sadrosadati, J. Gómez Luna, O. Mutlu | |||||||||||||||||||||||||||||
| Abstract | In this seminar course, we will cover fundamental and cutting-edge research papers in computer architecture. The course will consist of multiple components that are aimed at improving students' technical skills in computer architecture, critical thinking and analysis on computer architecture concepts, as well as technical presentation of concepts and papers in both spoken and written forms. | ||||||||||||||||||||||||||||||||
| Learning objective | The main objective is to learn how to rigorously analyze and present papers and ideas on computer architecture. We will have rigorous presentation and discussion of selected papers during lectures and a written report delivered by each student at the end of the semester. This course is for those interested in computer architecture. Registered students are expected to attend every lecture, participate in the discussion, and create a synthesis report at the end of the course. | ||||||||||||||||||||||||||||||||
| Content | Topics will center around computer architecture. We will, for example, discuss papers on hardware security; new execution paradigms like processing in memory; architectural acceleration mechanisms for key applications like machine learning, graph processing and bioinformatics; memory systems; interconnects; various fundamental and emerging paradigms in computer architecture; hardware/software co-design and cooperation; fault tolerance; energy efficiency; heterogeneous and parallel systems; technology scaling; new execution models, etc. See https://safari.ethz.ch/architecture_seminar for past examples. | ||||||||||||||||||||||||||||||||
| Lecture notes | All the materials will be posted on the course website: https://safari.ethz.ch/architecture_seminar/ Links to past course materials, including the synthesis report assignment, can be found in this page: https://safari.ethz.ch/architecture_seminar | ||||||||||||||||||||||||||||||||
| Literature | Key papers and articles, on both fundamentals and cutting-edge topics in computer architecture will be provided and discussed. These will be posted on the course website. See https://safari.ethz.ch/architecture_seminar for past examples. | ||||||||||||||||||||||||||||||||
| Prerequisites / Notice | Digital Design and Computer Architecture OR Digital Circuits / Computer Engineering Students should (1) have done very well in Digital Design and Computer Architecture , Digital Circuits or a similar course and (2) show a genuine interest in Computer Architecture. | ||||||||||||||||||||||||||||||||