227-0147-10L  VLSI 3: Full-Custom Digital Circuit Design

Courses

Catalogue data

Abstract	This third course in our VLSI series is concerned with full-custom digital integrated circuits. The goals include learning the design of digital circuits on the schematic, layout, gate, and register-transfer levels. The use of state-of-the-art CAD software (Cadence Virtuoso) in order to simulate, optimize, and characterize digital circuits is another important topic of this course.
Learning objective	At the end of this course, you will • understand the design of the main building blocks of state-of-the-art digital integrated circuits • be able to design and optimize digital integrated circuits on the schematic, layout, and gate levels • be able to use standard industry software (Cadence Virtuoso) for drawing, simulating, and characterizing digital circuits • understand the performance trade-offs between delay, area, and power consumption
Content	The third VLSI course begins with the basics of metal-oxide-semiconductor (MOS) field-effect transistors (FETs) and moves up the stack towards logic gates and increasingly complex digital circuit structures. The topics of this course include: • Nanometer MOSFETs • Static and dynamic behavior of complementary MOS (CMOS) inverters • CMOS gate design, sizing, and timing • Full-custom standard-cell design • Wire models and parasitics • Latch and flip-flop circuits • Gate-level timing analysis and optimization • Static and dynamic power consumption; low-power techniques • Alternative logic styles (dynamic logic, pass-transistor logic, etc.) • Arithmetic and logic circuits • Fixed-point and floating-point arithmetic • Synchronous and asynchronous design principles • Memory circuits (ROM, SRAM, and DRAM) • In- and near-memory processing architectures • Full-custom accelerator circuits for machine learning The exercises are concerned with schematic entry, layout, and simulation of digital integrated circuits using a disciplined standard-cell-based approach with Cadence Virtuoso.
Literature	N. H. E. Weste and D. M Harris, CMOS VLSI Design: A Circuits and Systems Perspective (4th Ed.), Addison-Wesley
Prerequisites / Notice	VLSI 3 can be taken in parallel with “VLSI 1: HDL-based design for FPGAs” and is designed to complement the topics of this course. Basic analog circuit knowledge is required.
Competencies	Subject-specific Competencies Concepts and Theories assessed Techniques and Technologies assessed Method-specific Competencies Analytical Competencies assessed Problem-solving assessed

Performance assessment

Performance assessment information (valid until the course unit is held again)
Performance assessment as a semester course
ECTS credits	6 credits
Examiners	C. Studer, O. Castañeda Fernández
Type	session examination
Language of examination	English
Repetition	The performance assessment is only offered in the session after the course unit. Repetition only possible after re-enrolling.
Mode of examination	written 120 minutes
Additional information on mode of examination	The exercises are an essential part of this course. If at least 6 out of the 11 exercises are successfully submitted in time, then the grade of the session exam will be increased by 0.25 points.
Written aids	Student's own hand-written summary: max. 3 A4-sized papers (6 sides). Calculators without communication abilities are allowed; otherwise, no electronic help is permitted.
This information can be updated until the beginning of the semester; information on the examination timetable is binding.

Learning materials

Groups

Restrictions

Offered in

Programme	Section	Type
Electrical Engineering and Information Technology Master	Advanced Core Courses	W
Electrical Engineering and Information Technology Master	Core Subjects	W
Electrical Engineering and Information Technology Master	Recommended Subjects	W
Electrical Engineering and Information Technology Master	Specialisation Courses	W
Physics Master	General Electives	W
Computational Science and Engineering Bachelor	Electives	W
Computational Science and Engineering Master	Electives	W